1. Field of the Invention
This invention relates to a semiconductor device having a multilayer interconnect structure including pads.
2. Background Art
Device downsizing in recent years has achieved high-speed operation of circuits. In addition, the progress of multilayer interconnection technology has enabled a number of metal layers to be laminated as interconnects. This inevitably increases metal layers constituting pads or connecting electrodes. As a result, the capacitance between metal layers and the pad-substrate capacitance have become not negligible. In this technical background, approaches to reducing pad capacitance have been increasingly required.
In this context, a large capacitance of pads has a problem of preventing high-speed operation of circuits. More specifically, interconnects have resistance in general. Thus the interconnect resistance and pad capacitance act as a low-pass filter (LPF), which cuts off high-frequency components and slows down the circuit operation. The characteristic frequency f of a low-pass filter is given by the following formula:f=1/(2nRC)  (1)where R denotes the interconnect resistance and C the pad capacitance. It is seen from equation (1) that when the interconnect resistance R remains constant, the operating frequency decreases as the pad capacitance C increases. That is, large capacitance prevents high-speed operation of circuits.
In a conventional semiconductor device having a multilayer interconnect structure, semiconductor elements and integrated circuits are formed on a semiconductor substrate made of silicon or the like. These integrated circuits and other elements are electrically connected to the exterior through pads constituting a multilayer interconnect structure formed on the semiconductor substrate. That is, pads are formed in each metal interconnect layer of the multilayer interconnect structure. Current is allowed to flow from the pad formed in the top layer of the multilayer interconnect structure to the inside of the semiconductor substrate. The multilayer interconnect structure has at least two metal interconnect layers on the semiconductor substrate, and the metal interconnect layers are mutually isolated by a plurality of interlayer insulating films. Pads in upper and lower layers are electrically interconnected by a plurality of vias (contacts) formed in the interlayer insulating films. The pads of the respective layers have the same size. A wire serving as an external terminal is bonded to the pad of the top layer.
JP 2003-510843T discloses a conventional technology in which a gate or other electrode is connected via a test pad to a set of parallel fingers in a bonding pad. This arrangement can address a large misalignment in the bonding process while still achieving connection of the bonding pad portions.